"Synthesis and Verification of Digital Circuits using Functional Simulation ..."

Stephen M. Plaza (2008)

> Home

Details and statistics

DOI: —

access: closed

type: Book or Thesis

metadata version: 2022-05-04

- view
  - electronic edition via handle.net
- export record
  dblp key:
  - phd/us/Plaza08
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/phd/us/Plaza08
Stephen M. Plaza:
Synthesis and Verification of Digital Circuits using Functional Simulation and Boolean Satisfiability. University of Michigan, USA, 2008

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.