"Power-constrained aware and latency-aware microarchitectural optimizations ..."

Sudhanshu Shekhar Jha (2016)

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metadata version: 2022-09-27

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Sudhanshu Shekhar Jha:
Power-constrained aware and latency-aware microarchitectural optimizations in many-core processors. Polytechnic University of Catalonia, Spain, 2016

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