"Timing analysis for hierarchical VLSI designs and high-level synthesis."

Prasert Kanthamanon (1997)

> Home

Details and statistics

DOI: —

access: closed

type: Book or Thesis

metadata version: 2018-11-13

- view
  - electronic edition @ unsw.edu.au
  authority control:
- export record
  dblp key:
  - phd/basesearch/Kanthamanon97
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/phd/basesearch/Kanthamanon97
Prasert Kanthamanon:
Timing analysis for hierarchical VLSI designs and high-level synthesis. University of New South Wales, Sydney, Australia, 1997

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.