"An Efficient Hardware Architecture for High Throughput AES Encryptor Using ..."

S. Sridevi Sathya Priya et al. (2017)

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DOI: 10.1007/S11277-016-3385-7

access: closed

type: Journal Article

metadata version: 2021-10-14

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S. Sridevi Sathya Priya, P. Karthigaikumar, N. M. Siva Mangai, P. Kirti Gaurav Das:
An Efficient Hardware Architecture for High Throughput AES Encryptor Using MUX Based Sub Pipelined S-Box. Wirel. Pers. Commun. 94(4): 2259-2273 (2017)

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