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"Stride Permutation Networks for Array Processors."

Tuomas Järvinen et al. (2007)

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DOI: 10.1007/S11265-006-0031-8

access: closed

type: Journal Article

metadata version: 2020-05-20

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  dblp key:
  - journals/vlsisp/JarvinenSST07
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  - https://dblp.org/rec/journals/vlsisp/JarvinenSST07
Tuomas Järvinen, Perttu Salmela, Harri Sorokin, Jarmo Takala:
Stride Permutation Networks for Array Processors. J. VLSI Signal Process. 49(1): 51-71 (2007)

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