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"Pipeline interleaving design for FIR, IIR, and FFT array processors."

Liang-Gee Chen, Yeu-Shen Jehng, Tzi-Dar Chiueh (1995)

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DOI: 10.1007/BF02120033

access: closed

type: Journal Article

metadata version: 2020-05-20

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  - journals/vlsisp/ChenJC95
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  - https://dblp.org/rec/journals/vlsisp/ChenJC95
Liang-Gee Chen, Yeu-Shen Jehng, Tzi-Dar Chiueh:
Pipeline interleaving design for FIR, IIR, and FFT array processors. J. VLSI Signal Process. 10(3): 275-293 (1995)

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