"Pipelined VLSI Architecture using CORDIC for Transform Domain Equalizer."

Ayan Banerjee, Anindya Sundar Dhar (2013)

> Home

Details and statistics

DOI: 10.1007/S11265-012-0657-7

access: closed

type: Journal Article

metadata version: 2023-08-21

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/vlsisp/BanerjeeD13
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/vlsisp/BanerjeeD13
Ayan Banerjee, Anindya Sundar Dhar:
Pipelined VLSI Architecture using CORDIC for Transform Domain Equalizer. J. Signal Process. Syst. 70(1): 39-48 (2013)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.