"An Efficient Test Pattern Generation Scheme for an On Chip BIST."

B. K. S. V. L. Varaprasad et al. (2001)

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DOI: 10.1155/2001/45324

access: open

type: Journal Article

metadata version: 2023-05-08

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B. K. S. V. L. Varaprasad, L. M. Patnaik, Hirisave S. Jamadagni, V. K. Agrawal:
An Efficient Test Pattern Generation Scheme for an On Chip BIST. VLSI Design 12(4): 551-562 (2001)

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