"Circuit Partitioning for FPGAs by the Optimal Circuit Reduction Method."

Roman P. Bazylevych, R. A. Melnyk, O. G. Rybak (2000)

> Home

Details and statistics

DOI: 10.1155/2000/58485

access: open

type: Journal Article

metadata version: 2023-05-08

- view
  - electronic edition via DOI (open access)
  authority control:
- export record
  dblp key:
  - journals/vlsi/BazylevychMR00
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/vlsi/BazylevychMR00
Roman P. Bazylevych, R. A. Melnyk, O. G. Rybak:
Circuit Partitioning for FPGAs by the Optimal Circuit Reduction Method. VLSI Design 11(3): 237-248 (2000)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.