Stop the war!

Остановите войну!

for scientists:

default search action

combined dblp search
author search
venue search
publication search

ask others

"Speed/Area-Efficient ECC Processor Implementation Over GF(2m) ..."

Medien Zeghid et al. (2023)

> Home

Details and statistics

DOI: 10.1109/TVLSI.2023.3268999

access: closed

type: Journal Article

metadata version: 2023-08-05

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/tvlsi/ZeghidACS23
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/tvlsi/ZeghidACS23
Medien Zeghid, Hassan Yousif Ahmed, Abdellah Chehri, Anissa Sghaier:
Speed/Area-Efficient ECC Processor Implementation Over GF(2^m) on FPGA via Novel Algorithm-Architecture Co-Design. IEEE Trans. Very Large Scale Integr. Syst. 31(8): 1192-1203 (2023)

a service of

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.