"Bit-Level Disturbance-Aware Memory Partitioning for Parallel Data Access ..."

Shouyi Yin et al. (2018)

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DOI: 10.1109/TVLSI.2018.2862388

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type: Journal Article

metadata version: 2020-03-11

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Shouyi Yin, Tianyi Lu, Zhicong Xie, Leibo Liu, Shaojun Wei:
Bit-Level Disturbance-Aware Memory Partitioning for Parallel Data Access for MLC STT-RAM. IEEE Trans. Very Large Scale Integr. Syst. 26(11): 2345-2357 (2018)

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