"Clock-delayed domino for dynamic circuit design."

Gin Yee, Carl Sechen (2000)

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DOI: 10.1109/92.863622

access: closed

type: Journal Article

metadata version: 2020-03-11

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Gin Yee, Carl Sechen:
Clock-delayed domino for dynamic circuit design. IEEE Trans. Very Large Scale Integr. Syst. 8(4): 425-430 (2000)

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