"Double-Node-Upset-Resilient Latch Design for Nanoscale CMOS Technology."

Aibin Yan et al. (2017)

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DOI: 10.1109/TVLSI.2017.2655079

access: closed

type: Journal Article

metadata version: 2020-03-11

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  - https://dblp.org/rec/journals/tvlsi/YanHYXOL17
Aibin Yan, Zhengfeng Huang, Maoxiang Yi, Xiumin Xu, Yiming Ouyang, Huaguo Liang:
Double-Node-Upset-Resilient Latch Design for Nanoscale CMOS Technology. IEEE Trans. Very Large Scale Integr. Syst. 25(6): 1978-1982 (2017)

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