"High-Density RAM/ROM Macros Using CMOS Gate-Array Base Cells: Hierarchical ..."

Nobutaro Shibata, Yoshinori Gotoh (2015)

> Home

Details and statistics

DOI: 10.1109/TVLSI.2014.2341352

access: closed

type: Journal Article

metadata version: 2020-03-11

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/tvlsi/ShibataG15
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/tvlsi/ShibataG15
Nobutaro Shibata, Yoshinori Gotoh:
High-Density RAM/ROM Macros Using CMOS Gate-Array Base Cells: Hierarchical Verification Technique for Reducing Design Cost. IEEE Trans. Very Large Scale Integr. Syst. 23(8): 1415-1428 (2015)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.