"An Effective Gated Clock Tree Design Based on Activity and Register Aware ..."

Weixiang Shen et al. (2010)

> Home

Details and statistics

DOI: 10.1109/TVLSI.2009.2030156

access: closed

type: Journal Article

metadata version: 2020-03-11

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/tvlsi/ShenCHH10
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/tvlsi/ShenCHH10
Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu:
An Effective Gated Clock Tree Design Based on Activity and Register Aware Placement. IEEE Trans. Very Large Scale Integr. Syst. 18(12): 1639-1648 (2010)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.