"Glitch-Optimized Circuit Blocks for Low-Power High-Performance Booth ..."

Anuradha Chathuranga Ranasinghe, Sabih H. Gerez (2020)

> Home

Details and statistics

DOI: 10.1109/TVLSI.2020.3009239

access: closed

type: Journal Article

metadata version: 2020-09-19

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/tvlsi/RanasingheG20
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/tvlsi/RanasingheG20
Anuradha Chathuranga Ranasinghe, Sabih H. Gerez:
Glitch-Optimized Circuit Blocks for Low-Power High-Performance Booth Multipliers. IEEE Trans. Very Large Scale Integr. Syst. 28(9): 2028-2041 (2020)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.