"Resynthesis of combinational logic circuits for improved path delay fault ..."

Irith Pomeranz, Sudhakar M. Reddy (2001)

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DOI: 10.1109/92.953501

access: closed

type: Journal Article

metadata version: 2020-03-11

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Irith Pomeranz, Sudhakar M. Reddy:
Resynthesis of combinational logic circuits for improved path delay fault testability using comparison units. IEEE Trans. Very Large Scale Integr. Syst. 9(5): 679-689 (2001)

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