"Energy optimization of multilevel cache architectures for RISC and CISC ..."

Uming Ko, Poras T. Balsara, Ashwini K. Nanda (1998)

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DOI: 10.1109/92.678891

access: closed

type: Journal Article

metadata version: 2020-03-11

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Uming Ko, Poras T. Balsara, Ashwini K. Nanda:
Energy optimization of multilevel cache architectures for RISC and CISC processors. IEEE Trans. Very Large Scale Integr. Syst. 6(2): 299-308 (1998)

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