"Parallel interleaver design and VLSI architecture for low-latency MAP ..."

Rostislav (Reuven) Dobkin, Michael Peleg, Ran Ginosar (2005)

> Home

Details and statistics

DOI: 10.1109/TVLSI.2004.842916

access: closed

type: Journal Article

metadata version: 2020-03-11

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/tvlsi/DobkinPG05
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/tvlsi/DobkinPG05
Rostislav (Reuven) Dobkin, Michael Peleg, Ran Ginosar:
Parallel interleaver design and VLSI architecture for low-latency MAP turbo decoders. IEEE Trans. Very Large Scale Integr. Syst. 13(4): 427-438 (2005)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.