"Certified timing verification and the transition delay of a logic circuit."

Srinivas Devadas et al. (1994)

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DOI: 10.1109/92.311642

access: closed

type: Journal Article

metadata version: 2023-09-30

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Srinivas Devadas, Kurt Keutzer, Sharad Malik, Albert R. Wang:
Certified timing verification and the transition delay of a logic circuit. IEEE Trans. Very Large Scale Integr. Syst. 2(3): 333-342 (1994)

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