"Scheduling tests for VLSI systems under power constraints."

Richard M. Chou, Kewal K. Saluja, Vishwani D. Agrawal (1997)

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DOI: 10.1109/92.585217

access: closed

type: Journal Article

metadata version: 2020-03-11

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Richard M. Chou, Kewal K. Saluja, Vishwani D. Agrawal:
Scheduling tests for VLSI systems under power constraints. IEEE Trans. Very Large Scale Integr. Syst. 5(2): 175-185 (1997)

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