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"A 2.5-ps Bin Size and 6.7-ps Resolution FPGA Time-to-Digital Converter ..."
Poki Chen et al. (2017)
- Poki Chen, Ya-Yun Hsiao, Yi-Su Chung, Wei Xiang Tsai, Jhih-Min Lin:
A 2.5-ps Bin Size and 6.7-ps Resolution FPGA Time-to-Digital Converter Based on Delay Wrapping and Averaging. IEEE Trans. Very Large Scale Integr. Syst. 25(1): 114-124 (2017)
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