"VeriGen: A Large Language Model for Verilog Code Generation."

Shailja Thakur et al. (2024)

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DOI: 10.1145/3643681

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type: Journal Article

metadata version: 2024-07-04

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Shailja Thakur, Baleegh Ahmad, Hammond Pearce, Benjamin Tan, Brendan Dolan-Gavitt, Ramesh Karri, Siddharth Garg:
VeriGen: A Large Language Model for Verilog Code Generation. ACM Trans. Design Autom. Electr. Syst. 29(3): 46:1-46:31 (2024)

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