"Processor verification using efficient reductions of the logic of ..."

Randal E. Bryant, Steven M. German, Miroslav N. Velev (2001)

> Home

Details and statistics

DOI: 10.1145/371282.371364

access: closed

type: Journal Article

metadata version: 2022-10-02

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/tocl/BryantGV01
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/tocl/BryantGV01
Randal E. Bryant, Steven M. German, Miroslav N. Velev:
Processor verification using efficient reductions of the logic of uninterpreted functions to propositional logic. ACM Trans. Comput. Log. 2(1): 93-134 (2001)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.