"RAPID: Memory-Aware NoC for Latency Optimized GPGPU Architectures."

Venkata Yaswanth Raparti, Sudeep Pasricha (2018)

> Home

Details and statistics

DOI: 10.1109/TMSCS.2018.2871094

access: closed

type: Journal Article

metadata version: 2025-01-19

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/tmscs/RapartiP18
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/tmscs/RapartiP18
Venkata Yaswanth Raparti, Sudeep Pasricha:
RAPID: Memory-Aware NoC for Latency Optimized GPGPU Architectures. IEEE Trans. Multi Scale Comput. Syst. 4(4): 874-887 (2018)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.