"Parallelization of WHILE loops on pipelined architectures."

Parthasarathy P. Tirumalai, Meng Lee, Michael S. Schlansker (1991)

> Home

Details and statistics

DOI: 10.1007/BF00127840

access: closed

type: Journal Article

metadata version: 2020-05-22

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/tjs/TirumalaiLS91
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/tjs/TirumalaiLS91
Parthasarathy P. Tirumalai, Meng Lee, Michael S. Schlansker:
Parallelization of WHILE loops on pipelined architectures. J. Supercomput. 5(2-3): 119-136 (1991)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.