"A Novel FPGA-Driven HD-SPWM Architecture With Zero-Sequence Voltage ..."

Rishiraj Sarker et al. (2024)

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DOI: 10.1109/TII.2024.3393566

access: closed

type: Journal Article

metadata version: 2024-10-03

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Rishiraj Sarker, Avik Bhattacharya, Sudipta Debnath, Alejandro Castillo Atoche, Asim Datta:
A Novel FPGA-Driven HD-SPWM Architecture With Zero-Sequence Voltage Insertion Strategy for Three-Level NPC Inverter. IEEE Trans. Ind. Informatics 20(9): 10814-10824 (2024)

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