"Modeling and Mitigating Transient Errors in Logic Circuits."

Ilia Polian et al. (2011)

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DOI: 10.1109/TDSC.2010.26

access: closed

type: Journal Article

metadata version: 2023-03-21

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  - https://dblp.org/rec/journals/tdsc/PolianHRB11
Ilia Polian, John P. Hayes, Sudhakar M. Reddy, Bernd Becker:
Modeling and Mitigating Transient Errors in Logic Circuits. IEEE Trans. Dependable Secur. Comput. 8(4): 537-547 (2011)

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