"Hierarchical Verification of Asynchronous Circuits Using Temporal Logic."

Bhubaneswaru Mishra, Edmund M. Clarke (1985)

> Home

Details and statistics

DOI: 10.1016/0304-3975(85)90223-3

access: open

type: Journal Article

metadata version: 2021-02-17

- view
  - electronic edition via DOI (open access)
  authority control:
- export record
  dblp key:
  - journals/tcs/MishraC85
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/tcs/MishraC85
Bhubaneswaru Mishra, Edmund M. Clarke:
Hierarchical Verification of Asynchronous Circuits Using Temporal Logic. Theor. Comput. Sci. 38: 269-291 (1985)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.