"A 1.05-to-3.2 GHz All-Digital PLL for DDR5 Registering Clock Driver With a ..."

Yeonggeun Song et al. (2022)

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DOI: 10.1109/TCSII.2021.3123610

access: closed

type: Journal Article

metadata version: 2022-04-01

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Yeonggeun Song, Han-Gon Ko, Changhyun Kim, Deog-Kyoon Jeong:
A 1.05-to-3.2 GHz All-Digital PLL for DDR5 Registering Clock Driver With a Self-Biased Supply-Noise-Compensating Ring DCO. IEEE Trans. Circuits Syst. II Express Briefs 69(3): 759-763 (2022)

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