"A 2.5 GS/s 7-Bit 5-Way Time-Interleaved SAR ADC With On-Chip Background ..."

Kiho Seong et al. (2022)

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DOI: 10.1109/TCSII.2022.3188290

access: closed

type: Journal Article

metadata version: 2022-10-18

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Kiho Seong, Jae-Soub Han, Yong Shim, Kwang-Hyun Baek:
A 2.5 GS/s 7-Bit 5-Way Time-Interleaved SAR ADC With On-Chip Background Offset and Timing-Skew Calibration. IEEE Trans. Circuits Syst. II Express Briefs 69(10): 4043-4047 (2022)

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