"A 119.64 GOPs/W FPGA-Based ResNet50 Mixed-Precision Accelerator Using the ..."

Yaozhong Ou et al. (2024)

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DOI: 10.1109/TCSII.2024.3377356

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type: Journal Article

metadata version: 2024-06-25

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Yaozhong Ou, Wei-Han Yu, Ka-Fai Un, Chi-Hang Chan, Yan Zhu:
A 119.64 GOPs/W FPGA-Based ResNet50 Mixed-Precision Accelerator Using the Dynamic DSP Packing. IEEE Trans. Circuits Syst. II Express Briefs 71(5): 2554-2558 (2024)

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