"A 2.5-5.0-GHz Clock Multiplier With 3.2-4.5-mUIrms Jitter and ..."

Jaya Deepthi Bandarupalli, Saurabh Saxena (2022)

> Home

Details and statistics

DOI: 10.1109/TCSII.2022.3177885

access: closed

type: Journal Article

metadata version: 2022-09-22

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/tcasII/BandarupalliS22
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/tcasII/BandarupalliS22
Jaya Deepthi Bandarupalli, Saurabh Saxena:
A 2.5-5.0-GHz Clock Multiplier With 3.2-4.5-mUI_rms Jitter and 0.98-1.06 mW/GHz in 65-nm CMOS. IEEE Trans. Circuits Syst. II Express Briefs 69(9): 3714-3718 (2022)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.