"A 10.8-to-37.4 Gb/s Reference-Less FD-Less Single-Loop Quarter-Rate ..."

Lin Wang et al. (2023)

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DOI: 10.1109/TCSI.2023.3263963

access: closed

type: Journal Article

metadata version: 2023-07-13

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Lin Wang, Yong Chen, Chaowei Yang, Xiaoteng Zhao, Pui-In Mak, Franco Maloberti, Rui Paulo Martins:
A 10.8-to-37.4 Gb/s Reference-Less FD-Less Single-Loop Quarter-Rate Bang-Bang Clock and Data Recovery Employing Deliberate-Current- Mismatch Wide-Frequency-Acquisition Technique. IEEE Trans. Circuits Syst. I Regul. Pap. 70(7): 2637-2650 (2023)

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