"A Low-Power DCO Using Interlaced Hysteresis Delay Cells."

Chien-Ying Yu et al. (2012)

> Home

Details and statistics

DOI: 10.1109/TCSII.2012.2213357

access: closed

type: Journal Article

metadata version: 2020-05-27

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/tcas/YuCYL12
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/tcas/YuCYL12
Chien-Ying Yu, Ching-Che Chung, Chia-Jung Yu, Chen-Yi Lee:
A Low-Power DCO Using Interlaced Hysteresis Delay Cells. IEEE Trans. Circuits Syst. II Express Briefs 59-II(10): 673-677 (2012)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.