![](https://dblp.uni-trier.de./img/logo.320x120.png)
![search dblp search dblp](https://dblp.uni-trier.de./img/search.dark.16x16.png)
![search dblp](https://dblp.uni-trier.de./img/search.dark.16x16.png)
default search action
"A CMOS 8-Bit 1.6-GS/s DAC With Digital Random Return-to-Zero."
Wei-Hsin Tseng, Jieh-Tsorng Wu, Yung-Cheng Chu (2011)
- Wei-Hsin Tseng, Jieh-Tsorng Wu, Yung-Cheng Chu:
A CMOS 8-Bit 1.6-GS/s DAC With Digital Random Return-to-Zero. IEEE Trans. Circuits Syst. II Express Briefs 58-II(1): 1-5 (2011)
![](https://dblp.uni-trier.de./img/cog.dark.24x24.png)
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.