"Hardware-Efficient Systolization of DA-Based Calculation of Finite Digital ..."

Pramod Kumar Meher (2006)

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DOI: 10.1109/TCSII.2006.877277

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type: Journal Article

metadata version: 2020-05-27

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Pramod Kumar Meher:
Hardware-Efficient Systolization of DA-Based Calculation of Finite Digital Convolution. IEEE Trans. Circuits Syst. II Express Briefs 53-II(8): 707-711 (2006)

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