"A VLSI Efficient Programmable Power-of-Two Scaler for 2n-1, ..."

Jeremy Yung Shern Low, Chip-Hong Chang (2012)

> Home

Details and statistics

DOI: 10.1109/TCSI.2012.2206491

access: closed

type: Journal Article

metadata version: 2020-06-15

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/tcas/LowC12
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/tcas/LowC12
Jeremy Yung Shern Low, Chip-Hong Chang:
A VLSI Efficient Programmable Power-of-Two Scaler for 2ⁿ-1, 2ⁿ, 2ⁿ+1 RNS. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(12): 2911-2919 (2012)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.