"Hardware-Efficient Node Processing Unit Architectures for Flexible LDPC ..."

Peter Hailes et al. (2018)

> Home

Details and statistics

DOI: 10.1109/TCSII.2018.2807362

access: open

type: Journal Article

metadata version: 2020-05-27

- view
  - electronic edition via DOI (open access)
  authority control:
- export record
  dblp key:
  - journals/tcas/HailesXMAH18
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/tcas/HailesXMAH18
Peter Hailes, Lei Xu, Robert G. Maunder, Bashir M. Al-Hashimi, Lajos Hanzo:
Hardware-Efficient Node Processing Unit Architectures for Flexible LDPC Decoder Implementations. IEEE Trans. Circuits Syst. II Express Briefs 65-II(12): 1919-1923 (2018)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.