"A Hardware-Efficient Feedback Polynomial Topology for DPD Linearization of ..."

Chak-Fong Cheang, Pui-In Mak, Rui Paulo Martins (2018)

> Home

Details and statistics

DOI: 10.1109/TCSI.2017.2788082

access: closed

type: Journal Article

metadata version: 2020-08-06

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/tcas/CheangMM18
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/tcas/CheangMM18
Chak-Fong Cheang, Pui-In Mak, Rui Paulo Martins:
A Hardware-Efficient Feedback Polynomial Topology for DPD Linearization of Power Amplifiers: Theory and FPGA Validation. IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(9): 2889-2902 (2018)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.