"CHAMP: Chip Floor Plan for Hierarchical VLSI Layout Design."

Kazuhiro Ueda, Hitoshi Kitazawa, Ikuo Harada (1985)

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DOI: 10.1109/TCAD.1985.1270094

access: closed

type: Journal Article

metadata version: 2020-09-24

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Kazuhiro Ueda, Hitoshi Kitazawa, Ikuo Harada:
CHAMP: Chip Floor Plan for Hierarchical VLSI Layout Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 4(1): 12-22 (1985)

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