"Block-Level Hardware Logic Simulation Machine."

Shigeru Takasaki et al. (1987)

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DOI: 10.1109/TCAD.1987.1270245

access: closed

type: Journal Article

metadata version: 2020-09-24

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Shigeru Takasaki, Tohru Sasaki, Nobuyoshi Nomizu, Nobuhiko Koike, Kenji Ohmori:
Block-Level Hardware Logic Simulation Machine. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 6(1): 46-54 (1987)

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