"Incorporating interconnect, register, and clock distribution delays into ..."

Tolga Soyata, Eby G. Friedman, James H. Mulligan Jr. (1997)

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DOI: 10.1109/43.559335

access: closed

type: Journal Article

metadata version: 2020-09-24

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Tolga Soyata, Eby G. Friedman, James H. Mulligan Jr.:
Incorporating interconnect, register, and clock distribution delays into the retiming process. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(1): 105-120 (1997)

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