"Self-Assertion-Based Countermeasures Within a RISC-V Microprocessor for ..."

Idris Somoye et al. (2024)

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DOI: 10.1109/TCAD.2024.3351592

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type: Journal Article

metadata version: 2024-06-18

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Idris Somoye, Tom J. Mannos, Brian Dziki, Jim Plusquellic:
Self-Assertion-Based Countermeasures Within a RISC-V Microprocessor for Coverage of Information Leakage Faults. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 43(6): 1677-1690 (2024)

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