"Verification at RTL Using Separation of Design Concerns."

Maya H. Safieddine et al. (2019)

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DOI: 10.1109/TCAD.2018.2848589

access: closed

type: Journal Article

metadata version: 2023-09-30

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  - https://dblp.org/rec/journals/tcad/SafieddineZKER19
Maya H. Safieddine, Fadi A. Zaraket, Rouwaida Kanj, Ali S. Elzein, Wolfgang Roesner:
Verification at RTL Using Separation of Design Concerns. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 38(8): 1529-1542 (2019)

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