"A Data-Driven Verilog-A ReRAM Model."

Ioannis Messaris et al. (2018)

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DOI: 10.1109/TCAD.2018.2791468

access: closed

type: Journal Article

metadata version: 2022-10-04

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Ioannis Messaris, Alexander Serb, Spyros Stathopoulos, Ali Khiat, Spyridon Nikolaidis, Themistoklis Prodromakis:
A Data-Driven Verilog-A ReRAM Model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(12): 3151-3162 (2018)

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