"A logic-to-logic comparator for VLSI layout verification."

Peter M. Maurer, Alexander D. Schapira (1988)

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DOI: 10.1109/43.3221

access: closed

type: Journal Article

metadata version: 2020-09-24

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Peter M. Maurer, Alexander D. Schapira:
A logic-to-logic comparator for VLSI layout verification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 7(8): 897-907 (1988)

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