"TriZone: A Design of MLC STT-RAM Cache for Combined Performance, Energy, ..."

Zihao Liu et al. (2018)

> Home

Details and statistics

DOI: 10.1109/TCAD.2017.2783860

access: closed

type: Journal Article

metadata version: 2022-07-04

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/tcad/LiuMLWWCLWPG18
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/tcad/LiuMLWWCLWPG18
Zihao Liu, Mengjie Mao, Tao Liu, Xue Wang, Wujie Wen, Yiran Chen, Hai Li, Danghui Wang, Yukui Pei, Ning Ge:
TriZone: A Design of MLC STT-RAM Cache for Combined Performance, Energy, and Reliability Optimizations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(10): 1985-1998 (2018)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.