"Graph-Optimization Techniques for IC Layout and Compaction."

Gershon Kedem, Hiroyuki Watanabe (1984)

> Home

Details and statistics

DOI: 10.1109/TCAD.1984.1270052

access: closed

type: Journal Article

metadata version: 2020-09-24

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/tcad/KedemW84
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/tcad/KedemW84
Gershon Kedem, Hiroyuki Watanabe:
Graph-Optimization Techniques for IC Layout and Compaction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 3(1): 12-20 (1984)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.