"Validatable nonrobust delay-fault testable circuits via logic synthesis."

Srinivas Devadas, Kurt Keutzer (1992)

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DOI: 10.1109/43.180267

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type: Journal Article

metadata version: 2020-09-24

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Srinivas Devadas, Kurt Keutzer:
Validatable nonrobust delay-fault testable circuits via logic synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(12): 1559-1573 (1992)

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